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TRF7970A
www.ti.com
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
Table 6-5. RX Special Setting Register (0x0A)
Function: Sets the gains and filters directly
Default: 0x40 at POR = H or EN = L, and at each write to the ISO Control register 0x01. When bits B7, B6, B5 and B4 are all zero, the
filters are set for ISO14443B (240 kHz to 1.4 MHz).
Bit
B7
B6
B5
B4
Name
C212
C424
M848
hbt
Function
Bandpass 110 kHz to 570 kHz
Bandpass 200 kHz to 900 kHz
Bandpass 450 kHz to 1.5 MHz
Bandpass 100 kHz to 1.5 MHz
Gain reduced for 18 dB
Description
Appropriate for 212-kHz subcarrier system (FeliCa)
Appropriate for 424-kHz subcarrier used in ISO15693
Appropriate for Manchester-coded 848-kHz subcarrier used in ISO14443A
and B
Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO14443
B3
gd1
00
= Gain
reduction
0 dB
B2
gd2
01
10
11
= Gain
= Gain
= Gain
reduction
reduction
reduction
for 5 dB
for 10 dB
for 15 dB
Sets the RX gain reduction, and reduces sensitivity
AGC activation level changed from five times the digitizing level to three
B1
agcr
AGC activation level change
times the digitizing level.
1 = 3x
0 = 5x
AGC action can be done any time during receive process. It is not limited
B0
no-lim
AGC action is not limited in time
to the start of receive ("max hold").
1 = continuously – no time limit
0 = 8 subcarrier pulses
Table 6-5 shows the various settings for the receiver analog section. It is important to note that setting B4,
B5, B6, and B7 to 0 results to a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for
ISO14443B 106 kbps, ISO14443A/B data-rates of 212 kbps and 424 kbps and FeliCa 424 kbps.
6.5
Receiver – Digital Section
The output of the TRF7970A analog receiver block is a digitized subcarrier signal and is the input to the
digital receiver block. This block includes a Protocol Bit Decoder section and the Framing Logic section.
The protocol bit decoders convert the subcarrier coded signal into a serial bit stream and a data clock.
The decoder logic is designed for maximum error tolerance. This enables the decoder section to
successfully decode even partly corrupted subcarrier signals that otherwise would be lost due to noise or
interference.
In the framing logic section, the serial bit stream data is formatted in bytes. Special signals such as the
start of frame (SOF), end of frame (EOF), start of communication, and end of communication are
automatically removed. The parity bits and CRC bytes are also checked and removed. This "clean" data is
then sent to the
127-byte FIFO register where it can be read by the external microcontroller system. Providing the data this
way, in conjunction with the timing register settings of the TRF7970A means the firmware developer has
to know about much less of the finer details of the ISO protocols to create a very robust application,
especially in low cost platforms where code space is at a premium and high performance is still required.
The start of the receive operation (successfully received SOF) sets the IRQ-flags in the IRQ and Status
register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13
(IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is
data to be read from the FIFO. The FIFO status register (0x1C) should be used to provide the number of
bytes that should be clocked out during the actual FIFO read.
Any error in the data format, parity, or CRC is detected and notified to the external system by an interrupt-
request pulse. The source condition of the interrupt request pulse is available in the IRQ status register
(0x0C). The main register controlling the digital part of the receiver is the ISO Control register (0x01). By
writing to this register, the user selects the protocol to be used. With each new write in this register, the
default presets are reloaded in all related registers, so no further adjustments in other registers are
needed for proper operation.
Copyright ? 2011–2014, Texas Instruments Incorporated
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